The present invention relates to an electronically programmable read only semiconductor memory cell of a type which is incorporated into an array of such cells formed on a semiconductor chip.
Nonvolatile memory devices offer the significant advantage over volatile memory devices that the information stored is not lost when power is removed. One example of a nonvolatile memory cell is a read only memory cell commonly referred to as a ROM. Information is introduced into a ROM during manufacture using a gate level mask or moat mask as set forth in U.S. Pat. No. 3,541,543 assigned to Texas Instruments. Such ROMS require masks in order to be programmed during manufacture. It is possible to avoid having to program ROM's during manufacture by using in place of ROM's electrically programmable ROM's or EPROMS. Various EPROM's have been developed such as that shown in U.S. Pat. No. 3,984,822 which employs a floating gate in a double level polysilicon MOS ROM. The floating gate is charged by injection of electrons from the channel and stays charged for years.
Electrically alterable ROM's have been developed as set forth in U.S. Pat. No. 3,881,180 issued Apr. 29, 1975, and U.S. Pat. No. 3,882,469 issued May 6, 1975 as well as application Ser. No. 644,982, filed Dec. 29, 1975, all by W. M. Gosney and assigned to Texas Instruments. The Gosney devices are floating gate cells with dual injection (both holes and electrons) so that the gates may be charged or discharged. Another electrically programmable and electrically alterable ROM is disclosed in U.S. Pat. No. 4,493,057 issued on Jan. 8, 1985 to David J. McElroy and assigned to Texas Instruments which uses a buried N.sup.+ diffusion region below a field oxide region as a transistor source region in order to reduce capacitive coupling between the source and an overlying column line. U.S. Pat. No. 4,246,592 issued Jan. 20, 1981 to Bartlett and U.S. Pat. No. 4,258,466 issued Mar. 31, 1981 to Kuo et al. and both assigned to Texas Instruments disclose buried diffused source and drain regions with a floating gate extending completely across the source/drain channel. Such devices have limited speed capability given the poor coupling between the second and first levels of polysilicon used for the floating gate and the control gate due to the relatively small ratio of floating gate to control gate area. Extending the edges of the floating gate over the top of the oxide isolation regions on either side of the channel provides an improved coupling between floating and control gates.
Accordingly, it is an object of the present invention to provide an improved electrically programmable read only memory device. Another object is to provide an EPROM having an improved coupling between the floating and control gates. An additional object is to provide an EPROM cell capable of being incorporated into a dense array of such cells.